Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.
Trends in portable electronic device design exacerbate the problem of limited available power. First, device form factors tend to shrink, due to increasing integration of electronics and miniaturization of component parts, such as disk drives. This forces the size of the battery to shrink as well, which generally reduces the available energy storage capacity. Second, electronic devices are increasingly sophisticated, offering new applications, more sophisticated user interfaces, enhancements such as encryption, and the like. The additional software implementing these features requires increased computational power to execute, which translates to larger, or additional, processors and more memory. Finally, successive generations of portable electronic device often add additional features such as various modes of wireless connectivity, which may require the integration of additional chip sets and other electronics. An increase in the demand for power by more processors and circuits, coupled with ever-shrinking battery size and capacity, has made power management a critical area of optimization for portable electronic device designers.
Several approaches to power management are known in the art. One such approach is to identify circuits (or sub-circuits) that are not used for extended periods, and put them into a low-activity state, also referred to as a “sleep mode,” even if other circuits in the device are fully active. As one example, the illuminated display screen of many devices will shut off after a (selectable) duration of no user interactivity. One way to shut down digital circuits is to isolate clocks signals from these circuits. Since storage elements within the digital circuits only change state in response to clock signal edges or levels, power-consuming electrical activity within the circuits effectively ceases.
A more sophisticated approach to the “sleep” technique is to match the frequency of a clock signal to the level of activity of a digital circuit. For example, a processor engaged in heavy computation may be clocked at a high frequency, to extract maximum performance. However, when the processor is performing merely background tasks, the frequency of its clock signal may be reduced without a user-noticeable degradation of performance, which concomitantly reduces the power consumed.
Another approach to power management is to vary the power supplied to various circuits (or sub-circuits) according to the instantaneous load of the circuit. In this manner, circuits that are engaged in computation or other activity are provided sufficient power to operate, and circuits experiencing a lighter load are provided with a lower level of current. This variable power supply approach is possible by dedicating switched mode power supplies to each circuit. As well known in the art, a switched mode power supply transfers discrete quanta of charge from a power source (such as a battery) into a power storage and integration device (such as an inductor or capacitor), from which the power is made available to the circuit. At high current loads, the power supply must switch charge at a higher frequency; at lower loads, a lower switching frequency will suffice. Thus, the power supply may vary the power provided to a circuit by changing its switching frequency.
Even when several discrete circuits of a portable electronic device are simultaneously active, it may be advantageous to balance the current drain from the battery over time—that is, reduce or eliminate current “surges” caused by simultaneous clocking of digital electronics in several independent circuits, and/or the simultaneous switching of charge from the battery by numerous power supplies. One way to achieve such balance is by staggering the relative phases of the clock signals distributed to the disparate circuits or power supplies.
A clock generation and management approach that provides flexibility in clock enablement, clock frequency, and relative phase for a plurality of discrete clock signals would be beneficial in power management for modern portable electronic devices. Simplistic approaches to such clock signal manipulation, however—such as simply “gating” clock signals with combinatorial logic—can produce “glitches,” or transient voltage spikes, in the generated clock signals. These glitches can randomly cause some—but not all—digital storage devices to change state, which may have disastrous consequences as processors, state machines, status registers, and the like are clocked into unknown and unintended states. Accordingly, the ability to precisely control and synchronously change the frequency and relative phase of a plurality of clock signals, without introducing any glitches in the generated clock signals, stands as a major challenge in power management for portable digital electronic devices.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.